OpenAI’s Hardware team builds AI-native silicon and systems for advanced AI workloads.
Role focuses on electrical architecture, modeling, optimization, and validation for high-speed
Specializes in 2.5D/3D SI/PI, PDN optimization, and SerDes/memory channel architecture.
Collaborates with ASIC, package, system, mechanical, thermal, power, and silicon validation teams.

🎯 Requirements

5+ years in signal integrity and power integrity, high-speed interconnect and PDN design.
Strong fundamentals in transmission lines, impedance, loss, crosstalk, return paths, PDN
Hands-on with electromagnetic/SI/PI tools: Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence
Experience with package layouts (Cadence APD/SIP) and automated design optimization flows.
Ability to communicate across ASIC, package, PCB, system, mechanical, thermal, power, validation

🎁 Benefits

Equity options in compensation package.
Competitive salary with equity value.

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