ASIC/SOC DFT Engineer (Silicon Engineering)

📋 Description

• Evaluate design readiness for scan insertion via RTL and DRC tools
• Integrate and verify DFT fabrics and IP within Subsystems
• Run and refine scan insertion through synthesis tools
• Perform ATPG analysis for scan chain quality and coverage
• Run and debug non-timing and SDF gate-level simulations
• Create ATPG content for post-silicon testing and verify with gate-level sim

🎯 Requirements

• Bachelor’s in EE, CE, or CS
• 1+ years of professional ASIC experience
• Experience in scan insertion or DFT setup