Design-for-Test (DFT) Engineer

📋 Description

• DFT engineer to drive design-for-test for ASIC/SoC designs
• Focus on ATPG, Scan architectures, test coverage and verification
• Collaborate with RTL, Physical Design, Verification, and Product Engineering

🎯 Requirements

• 5–20 years in DFT/ASIC design and test engineering
• ATPG (Automatic Test Pattern Generation) expertise
• Experience with Scan architecture and scan insertion
• Knowledge of scan chains, compression, test modes, and coverage
• Debug ATPG patterns, coverage issues, and DFT rule violations
• Strong scripting/automation (Tcl, Python, or Perl)

🎁 Benefits