Design-for-Test Engineer

📋 Description

• Define and implement DFT architectures for ASIC/SoC designs.
• Develop and integrate Scan-based DFT structures across blocks and top-level designs.
• Develop, run, and debug ATPG flows for fault models.

🎯 Requirements

• 5–20 years of hands-on experience in DFT/ASIC design and test engineering.
• Strong expertise in ATPG (Automatic Test Pattern Generation).
• Extensive experience with Scan architecture and Scan insertion.
• Understanding of scan chains, scan compression, test modes, and test coverage.
• Experience debugging ATPG patterns, coverage issues, and DFT rule violations.
• Team collaboration with RTL, synthesis, verification, and physical design.