Principal ASIC Design Engineer (Silicon Engineering)

📋 Description

• Develop next-generation ASICs for space and ground infrastructure in Starlink network
• Define micro-architecture and implement RTL in Verilog/SystemVerilog
• Collaborate with verification, physical design, and IP teams
• Provide timing constraints and support synthesis, timing closure, and formality checks
• Participate in silicon bring-up and validation

🎯 Requirements

• Bachelor’s in electrical/computer engineering or computer science
• 10+ years RTL implementation experience
• Experience with embedded CPU subsystems and standard bus protocols (e.g., AXI, AHB)
• Strong problem-solving skills for clock domain crossings and power optimization
• Proficiency with scripting (e.g., Python) and HDL tools
• Excellent team-player with ability to work independently

🎁 Benefits

• Competitive base salary with long-term incentives and stock options
• Comprehensive medical, vision, dental coverage
• 401(k) retirement plan and disability insurance
• Paid parental leave and generous vacation/holiday time