Senior Staff Engineer - Physical Design

📋 Description

• Lead physical design implementation from floorplanning to GDS signoff.
• Drive PPA and reliability optimization across nodes.
• Manage signoff closure for timing, power, area, and reliability.
• Collaborate with RTL, DFT, STA, package, and CAD teams.
• Improve physical design methodologies with automation and tooling.
• Support tape-out and provide technical leadership and mentorship.

🎯 Requirements

• Experience: 12+ years in ASIC/SoC physical design implementation.
• Education: Bachelor's or Master's in Electronics, Electrical Engineering, VLSI, or related field.
• EDA expertise: Cadence Innovus, Synopsys ICC2, PrimeTime, StarRC.
• Physical design: floorplanning, power planning, placement, clock-tree synthesis, routing, signoff.
• Timing & reliability: timing closure, low-power, signal integrity, IR/EM.
• Advanced nodes: 7nm/5nm/3nm experience preferred.

🎁 Benefits

• Remote-friendly setup in India with growth opportunities.
• Opportunity to work on AI/HPC semiconductor infrastructure.
• High-impact role with ownership over design methodologies.
• Fast-paced environment with focus on execution.
• Collaboration with experienced semiconductor professionals.
• Exposure to advanced tech nodes and chiplet architectures.