Senior Staff RTL Verification Engineer

Added
16 days ago
Type
Full time
Salary
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Related skills

python ci/cd systemverilog uvm coverage

📋 Description

  • Drive RTL verification activities for RAIN RFID Reader ICs across lifecycle.
  • Define verification methodologies, infrastructure, and processes.
  • Develop SystemVerilog testbenches, BFMs, models, checkers, and reusable sequences.
  • Create directed and constrained-random tests for full functional coverage.
  • Develop verification plans and coverage metrics for tape-out readiness.
  • Write SV assertions, coverage monitors, and automated checks.

🎯 Requirements

  • Bachelor’s in EE/CE or related field; 12+ yrs exp (or 8+ with MS, 5+ with PhD).
  • 12+ yrs RTL verification experience + tape-out/production.
  • Strong in verifying microcontroller microarchitectures and complex FSMs.
  • Proven ability to craft comprehensive RTL verification plans.
  • Hands-on with bus functional models, subsystem models, checkers, reusable infra.
  • SV and UVM expert; SVAs, coverage monitors, and coverage strategies.

🎁 Benefits

  • Competitive compensation: $158,700–$238,100 base salary.
  • Performance-based rewards: bonuses and stock-based comp.
  • Healthcare coverage and retirement savings (401(k) with match).
  • Remote work: Remote-eligible in the United States.
  • Open PTO and inclusive, collaborative culture.
  • Growth with advanced semiconductor tech and modern verification methods.
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