Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC
Optimize designs for power, performance and area
Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level
Contribute to continual improvements to our designs by building physical and digital tools to
Engage in high-level architectural design for test systems to support FPGA/ASIC validation
Collaborate with software engineers in developing production software for your designs

🎯 Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL

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