Design Verification Engineer (Silicon Engineering)

📋 Description

• Responsible for digital ASIC verification at block and system level
• Write and review test plans; develop test harnesses and sequences
• Develop SystemVerilog testbench infrastructure (UVM and non-UVM) for testing DSP blocks
• Execute test plans; run regressions; close code/functional coverage
• Automate test case generation with Python and MATLAB
• Contribute to pre-silicon verification, chip bring-up, and post-silicon validation

🎯 Requirements

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 1+ years of experience with design verification and test bench development
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Experience in constrained random verification
• ITAR: U.S. citizen/national or eligible for required authorizations

🎁 Benefits

• Medical, vision and dental coverage
• 401(k) retirement plan
• Short/long-term disability and life insurance
• Paid parental leave and employee discounts
• 3 weeks paid vacation and 10+ paid holidays
• Sick leave for exempt employees (5 days/year)