Design Verification Engineer (Silicon Engineering)

📋 Description

• Responsible for digital ASIC verification at block and system level.
• Write and review test plans, develop test harnesses and sequences.
• Develop SystemVerilog testbench infrastructure (UVM and non-UVM) for testing designs, including DSP blocks.
• Execute test plans, run regressions, and achieve code and functional coverage closure.
• Automate test case generation using Python and MATLAB.
• Contribute toward pre-silicon verification, chip bring-up and post-silicon validation.

🎯 Requirements

• Bachelor’s degree in electrical engineering, computer science or computer engineering.
• 1+ years of experience with design verification and test bench development.
• Experience with verification methodologies such as UVM.
• Strong object-oriented programming knowledge.
• Experience with scripting languages, e.g. Python for automation.
• RTL design, chip bring-up, and post-silicon validation experience.
• Ability to work extended hours and weekends as needed to meet milestones.
• Experience in constrained random verification.

🎁 Benefits

• Comprehensive medical, vision, and dental coverage.
• 401(k) retirement plan and disability insurance.
• Life insurance and paid parental leave.
• Vacation, holidays and sick leave allowances.
• Stock options and Employee Stock Purchase Plan.