Design Verification Engineer (Silicon Engineering)

Added
10 days ago
Type
Full time
Salary
Salary not provided

Related skills

python matlab systemverilog uvm constrained_random_verification
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๐Ÿ“‹ Description

  • Verify digital ASIC at block and system level
  • Write and review test plans; develop test harnesses and sequences
  • Develop SV testbench infra (UVM and non-UVM) for DSP blocks
  • Execute test plans; run regressions; ensure coverage closure
  • Automate test cases with Python and MATLAB
  • Contribute to pre-silicon verification, chip bring-up and post-silicon validation

๐ŸŽฏ Requirements

  • Advanced degree in electrical or computer engineering
  • Experience with verification methodologies such as UVM
  • Strong object-oriented programming knowledge
  • Experience in constrained random verification
  • Experience with test plans, coverage models, and analyzing results
  • Scripting with Python for automation
  • Ability to work extended hours and weekends to meet milestones
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