Design Verification Engineer (Silicon Engineering)

📋 Description

• Responsible for digital ASIC verification at block and system level
• Write and review test plans; develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (UVM and non-UVM) for DSP blocks
• Execute test plans; run regressions; code and functional coverage closure
• Automate test case generation using Python and MATLAB
• Contribute to pre-silicon verification, chip bring-up, and post-silicon validation
• Be a hands-on self-starter who can fully verify a complex digital design

🎯 Requirements

• Bachelor’s degree in Electrical Engineering, CS, or Computer Engineering
• 1+ years of design verification and test bench development experience
• Advanced degree in electrical or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs
• Ability to work extended hours and weekends as needed to meet milestones

🎁 Benefits

• Stock options and long-term incentives
• Medical, vision, and dental coverage
• 401(k) retirement plan
• Short- and long-term disability insurance
• Life insurance
• Paid parental leave
• Paid vacation and holidays; 3+ weeks vacation typical for exempt employees