Engineering Manager - FPGA & Hardware - Enforced Security

📋 Description

• Own the FPGA discipline for the NetWall line — RTL architecture, verification strategy, timing
• Select the silicon and the boards — evaluate FPGA families and COTS cards against sustained line
• Build the one-way datapath in gateware — framing, link supervision, no back-channel, fail-closed
• Move protocol termination into hardware — TCP state machines, and in time TLS termination and
• Own verification as a first-class deliverable — UVM environments, constrained-random regression
• Deliver the design independence that certification requires — two filter implementations on two

🎯 Requirements

• Five or more years in FPGA development, including production RTL in a shipping product and
• Deep SystemVerilog or VHDL, with genuine ownership of architecture, verification, and timing
• High-speed interface experience — multi-gigabit transceivers, Ethernet MAC and PCS, PCIe endpoints
• Demonstrated protocol implementation in hardware — parsing, state machines, or offload — not only
• Verification depth: UVM, constrained-random and coverage-driven methodology, and exposure to formal
• Fluent in at least one major toolchain — AMD Vivado or Altera Quartus Prime Pro — and able to stand

🎁 Benefits

• An installed base across energy, manufacturing, defense, government, transportation, and
• An existing Common Criteria EAL4+ certification to extend rather than earn, and certified optical
• An R&D organization of approximately 50 engineers, and the MetaDefender® platform —
• A funded multi-year program to take the line to 100 Gbps and to NCDSMO Raise the Bar
• Budget and hiring authority to build the FPGA team from the first engineer, outside the standard