FPGA/ASIC Design Engineer (Silicon Engineering)

📋 Description

• Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC
• Optimize designs for power, performance and area
• Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level
• Contribute to continual improvements to our designs by building physical and digital tools to
• Engage in high-level architectural design for test systems to support FPGA/ASIC validation
• Collaborate with software engineers in developing production software for your designs

🎯 Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
• 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL
• ASIC/FPGA system integration experience
• Proficiency in Python, C/C++, and Bash
• Experience in designing DSP, digital communication system datapath blocks, and/or modem design
• Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g.

🎁 Benefits

• Base salary range: $125,000.00 - $160,000.00 for Level 1
• Base salary range: $145,000.00 - $195,000.00 for Level 2
• Long-term incentives in the form of company stock or long-term cash awards
• Potential discretionary bonuses and ability to purchase additional stock at a discount through
• Comprehensive medical, vision, and dental coverage
• Access to a 401(k) retirement plan