FPGA Digital Design Engineer (6+ month Contract)

📋 Description

• Develop custom IP for new features of the Kepler satellite digital payloads
• Iterate on current DSP and interface designs to improve reliability
• Work with IP core vendors to integrate new functionality into the Kepler designs
• Work with lead engineers in developing the communications and network architecture of our future
• Participate in conceptual design studies of new spacecraft

🎯 Requirements

• Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent
• 5+ yr. working experience with FPGA/RTL design
• Verilog, SystemVerilog, or VHDL with the willingness to learn or pivot to SystemVerilog
• Xilinx FPGA(s). Specifically, Zynq and UltraScale
• Solid understanding of timing principles, including clock domain crossing and timing closure
• Strong scripting skills (e.g Python, Tcl, csh/bash, etc.)

🎁 Benefits

• Competitive compensation with a robust equity plan
• Comprehensive coverage for health, dental, and vision insurance—including dependents
• Unlimited vacation, supportive parental leave policy, and company-wide holiday shutdown
• Semi-annual company-wide parties and frequent in-office team events
• Relocation packages available for approved roles
• $1,500 annual professional development fund