Principal DFT Engineer (Silicon Engineering)

📋 Description

• Lead DFT architecture design and optimization (scan insertion, BIST) with Tessent.
• Own ATPG tools and patterns for stuck-at/transition/path-delay faults; post-silicon validation.
• Evaluate design readiness for scan insertion via RTL and physical design DRC checks.
• Integrate and verify DFT fabrics and IP within subsystems.
• Run and debug non-timing and SDF-annotated gate-level simulations.
• Develop test scripts and automation using Perl, Python, Tcl, or C++.

🎯 Requirements

• Bachelor’s degree in electrical/computer engineering or computer science.
• 10+ years experience with ASICs.
• 10+ years in scan insertion and DFT setup, integration and validation.
• Leadership in SOC DFT execution from concept to tapeout and deployment.
• RTL experience debugging DFT-related RTL connectivity.
• Solve clock domain crossings and power optimization.

🎁 Benefits

• Stock options and long-term incentives
• Medical, vision, and dental coverage
• 401(k) retirement plan
• Short and long-term disability and life insurance
• Paid parental leave
• Paid vacation and holidays