Principal DFT Engineer (Silicon Engineering)

📋 Description

• Lead DFT architecture implementation and optimization using Siemens Tessent.
• Own ATPG tools and pattern generation for stuck-at, transition, and path-delay faults.
• Evaluate scan insertion readiness via RTL and physical design DRC checks.
• Integrate and verify DFT fabrics and IP within Subsystems.
• Run and debug non-timing and SDF-annotated gate-level simulations.
• Develop test scripts in Perl, Python, Tcl, or C++ and analyze data.

🎯 Requirements

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 10+ years of experience working with ASICs.
• 10+ years in scan insertion and DFT setup, integration and validation.
• Leadership experience driving SOC DFT execution from concept through tapeout and product deployment.
• RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT.
• Experience with UPF, formal verification, and DRC rule checking.

🎁 Benefits

• Stock incentives and Employee Stock Purchase Plan.
• Medical, vision and dental coverage.
• 401(k) retirement plan with disability and life insurance.
• Paid parental leave and other perks.
• Three weeks of paid vacation plus 10+ holidays per year.