Lead DFT architecture implementation using Siemens Tessent for RTL and gate-netlist DFT
Develop ATPG patterns for stuck-at, transition, and path-delay faults; support post-silicon testing
Evaluate scan insertion readiness via RTL and physical design DRC tools
Integrate and verify DFT fabrics and IP within subsystems
Run and debug non-timing and SDF-annotated gate-level simulations
Develop test scripts; automate processes; analyze data with Perl, Python, Tcl, or C++

🎯 Requirements

Bachelor's degree in electrical or computer engineering or computer science
10+ years of experience working with ASICs
10+ years of experience in scan insertion and DFT setup, integration and validation
Leadership experience driving SOC DFT execution from concept through tapeout and product deployment

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