Principal Engineer, PHY/MAC Design (P)

📋 Description

• Develop end-to-end simulation frameworks for sophisticated wireless systems.
• Work spanning the full signal chain from propagation channel modeling and RF/antenna behavior to
• Develop and refine Digital Signal Processing engines for wireless communication systems.
• Develop micro-architecture, and System Verilog RTL to meet size, timing, and power target.
• Analyze, and identify bottlenecks in design and provide feedback on micro-architecture, and
• Develop, and refine design, verification and analysis tools and flows.

🎯 Requirements

• Masters degree in Electrical Engineering, or a related field, plus ten (10) years of relevant
• Experience in ASIC development and/or FPGA prototyping
• Experience in RTL design using Verilog, SystemVerilog
• Understanding of Digital Signal Processing theory, and mapping to design
• Experience in WiFi Physical Layer, or other Physical layer such as Cellular
• Experience with VCS, Verdi, Spyglass, or equivalent tools

🎁 Benefits

• Up to 15% domestic travel.