Architect and design next-gen storage hardware from schematic to PCB layout.
Lead hardware validation, including eDVT and system stress testing.
Perform deep root-cause analysis on hardware issues with high-speed scopes.
Optimize power, signal integrity, and thermal for PCIe and Ethernet up to 800Gbps.
Based in Santa Clara, CA; onsite work per policy.

🎯 Requirements

Hardware design mastery: schematic capture, PCB layout, x86, SI routing.
Systems engineering: compute/storage/I/O; SSDs, power supplies, VR circuits.
Automation & scripting: Python or Bash for test environments.
Protocol proficiency: PCIe, I2C, SPI; analyze protocol traces.

🎁 Benefits

Growth and development opportunities; Fortune Best Workplaces in Tech Bay Area.
Flexible time off, wellness resources, team events.
On-going recognition and a strong, inclusive team culture.

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