Research Engineer, Chip Design RL (Reinforcement Learning)

📋 Description

• Design RL environments and evaluations for RTL generation and verification.
• Optimize EDA tool latency and proxy rewards.
• Run experiments and shape the roadmap.
• Deliver results to research and production training runs.
• Collaborate with researchers and engineers across Anthropic.

🎯 Requirements

• ASIC/FPGA design: RTL, UVM, formal methods, PPA, DFT, ECOs.
• Proficient with industry EDA tools/processes.
• Taped out chips; from spec to silicon.
• Balance research exploration with engineering.
• Passion for safe, beneficial AI.
• Experience with reinforcement learning, evaluations or environments.

🎁 Benefits

• Competitive compensation and benefits.
• Optional equity donation matching.
• Generous vacation and parental leave.
• Flexible working hours.
• Office space in SF.