Collaborate with IC designers on chip floor plan, P/G distribution and pad locations.
Estimate layout schedule and flag complex areas early.
Layout RF/analog blocks with good matching and minimized parasitics.
Perform DRC, ERC, LVS checks and fix errors.
Top-level layout integration with ESD structures and pads; share GDS with foundry.
Work with EDA vendors to trial new tools and features.

🎯 Requirements

BS in Electrical/Computer Eng with 1+ yr IC layout exp, or 3+ yrs exp in lieu of degree
Strong analog layout skills
Experience with advanced nodes 22nm/16nm/7nm/5nm or below
RF block layout experience (LNA, VCO, mixers)
Scripting: Python/Perl/Shell
ITAR compliance and export controls

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