Work with IC designers to determine the chip floor plan and pad locations.
Estimate layout schedule and identify early complexity.
Layout of RF and analog blocks focusing on matching and parasitics.
Perform DRC/ER/LVS checks and resolve errors.
Top-level layout integration with ESD structures and pad assembly; final tape-out.
Coordinate with EDA suppliers to trial new tools and features.

🎯 Requirements

Bachelor's in EE/CE and 1+ year IC layout exp; or 3+ years in lieu of degree.
Strong analog layout skills.
Experience with advanced nodes: 22nm, 16nm, 7nm, 5nm or below.
Experience in RF circuit block layouts up to 50 GHz (LNA, VCO, mixers).
Experience with skill programming; shell scripting (Python/Perl); Linux; revision control.
Willing to work extended hours and weekends; ITAR/compliance may apply.

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