RTL Lead Engineer

📋 Description

• Own end-to-end RTL design for major subsystems or full-chip blocks
• Define micro-architecture aligned with PPA targets
• Lead and mentor a team of RTL engineers
• Drive design reviews, coding standards, and best practices
• Collaborate with DV, PD, STA/Timing/DFT teams
• Drive schedule, risk mitigation, and execution toward tapeout

🎯 Requirements

• Bachelor’s or Master’s in Electrical/Computer Engineering
• 10+ years ASIC/SoC RTL design experience
• SystemVerilog/Verilog RTL coding proficiency
• Micro-architecture design expertise
• Strong timing, CDC/RDC, UPF design knowledge
• Proven track record leading blocks through multiple tapeouts; synthesis with Design Compiler

🎁 Benefits

• On-site role in Bengaluru; five days on-site
• Leadership opportunity with RTL/SoC teams
• Work with a global semiconductor client base
• Close collaboration with DV, PD, STA/DFT teams
• Mentorship and career growth in a hardware-focused role