Senior Formal Verification Engineer

📋 Description

• Hybrid work schedule in Silicon Engineering Lead reporting line
• Work on formal verification strategy for first-pass silicon success
• Architect FV environments and reusable testbenches for multiple projects
• Drive continuous integration, regression flows, dashboards for status
• Lead and mentor verification engineers to adopt formal methods

🎯 Requirements

• BS/MS/PhD in CS/EE or related field, 5+ years in formal verification
• Proficiency with Cadence JasperGold, Synopsys VC Formal, or Mentor Questa Formal
• Strong C++ and/or Python skills
• Model complex designs in SystemVerilog with SVA
• Proven ability to apply formal debug techniques (clock domains, abstractions)
• Excellent communication to influence cross-functional teams

🎁 Benefits

• Waymo employees participate in discretionary bonus and equity
• Generous company benefits program
• Salary range: USD 204,000 – 259,000
• Hybrid/work flexibility and relocation assistance if applicable
• Opportunities for professional growth and aligned with Waymo’s mission