Senior RTL Engineer, Interconnect Design

📋 Description

• Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic, as well as off-chip protocol bridges and interfaces.
• Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and design integrity.
• Perform substantial direct microarchitecture and RTL coding work.
• Collaborate with architecture and design team members on the overall solution and execution plan for cutting-edge large-scale custom silicon.
• Work with performance and architecture teams to analyze traffic patterns, identify bottlenecks, and optimize interconnect behavior under realistic system workloads.
• Collaborate with design verification teams to develop verification strategies, coverage plans, assertions, stress scenarios, and debug approaches for highly concurrent fabric behavior.

🎯 Requirements

• Extensive industry experience designing and delivering complex SoC interconnect, NoC, coherent fabric, memory subsystem, cache-coherent, or chip-level integration solutions.
• A strong track record of owning major RTL blocks or SoC subsystems from microarchitecture through tape-out and silicon bring-up.
• Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.
• Strong understanding of interconnect concepts such as topology, routing, arbitration, virtual channels, flow control, buffering, ordering, quality of service, coherency, deadlock avoidance, congestion management, and performance monitoring.
• Experience with common on-chip or chip-to-chip protocols and interfaces, such as AXI, APB, CXL, PCIe, Ethernet.
• Experience building custom networking protocols or protocol extensions.

🎁 Benefits

• Hybrid work model with 3 days in the office per week.
• Relocation assistance for new employees.