Define top-level SoC architecture and subsystem partitioning.
Drive architecture tradeoffs for performance, power, area, bandwidth, latency.
Develop and review system architecture specs, interfaces, and microarchitecture.
Collaborate with RTL, verification, and design teams.
Lead performance modeling and workload analysis using C/C++/SystemC.
Define memory hierarchy, NoC/interconnect, coherency, and cache structures.

🎯 Requirements

B.S./M.S. in Electrical/Computer Engineering, CS, or related field.
10+ years in SoC architecture, ASIC or semiconductor design.
Strong understanding of modern SoC architectures and integration.
Experience with CPU/GPU/NPU architectures and NoC/interconnect.
Experience with PCIe, DDR5/LPDDR5X, Ethernet, memory systems.
RTL development and verification, plus architecture modeling tools.

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