SOC/IP Integration Engineer (eInfochips Inc)

📋 Description

• Lead the integration of system-on-chip subsystems using Verilog and SystemVerilog.
• Integrate first-party and third-party IP components, generate interconnect fabrics, perform
• Apply strong understanding of RTL design and digital design principles to evaluate integration
• Support synthesis activities, define and review timing constraints, consider floor-planning
• Drive design-quality activities including CDC, lint, RDC, and register integration checks.
• Investigate complex integration challenges, evaluate existing solutions, and resolve issues

🎯 Requirements

• Typically 5–7 years of relevant experience with a four-year degree, or at least 3 years with an
• Strong understanding of RTL design and digital logic concepts.
• Demonstrated experience integrating SoC subsystems and combining first-party and third-party IP
• Practical experience with Verilog and SystemVerilog.
• Knowledge of synthesis, timing constraints, floor-planning, and physical design handoff.
• Familiarity with CDC, lint, RDC, register integration, and design-quality checks.

🎁 Benefits

• Competitive compensation
• Medical, dental, and vision insurance
• 401(k) retirement plan with matching contributions
• Short-term and long-term disability insurance
• Health Savings Account (HSA) and Health Reimbursement Arrangement (HRA) options
• Paid leave including vacation, holidays, and sick time