Sr. Design for Test (DFT) Engineer

📋 Description

• Create chip/module/system-level DFT solutions for our photonics AI platform
• Develop and deploy DFT methodologies for next-generation products
• Provide architecture for integrated electronics/analog/digital test including ATPG and boundary scan
• Work with RTL designers to define front-end integration
• Work with physical-design engineers to provide backend integration
• Create automated flow that can scale with the team and company

🎯 Requirements

• Bachelor’s degree in Electrical or Computer Engineering or related field
• At least 5 years of DFT experience on advanced ASIC designs
• Proven experience in pre-silicon design activities
• Experience with Python or TCL scripting
• Solid understanding of DFT concepts such as Scan, ATPG, memory test, and JTAG
• Experience with commercial EDA DFT tools on MBIST, ATPG, and Boundary Scan

🎁 Benefits

• Comprehensive Health Care Plan (Medical, Dental & Vision)
• Retirement Savings Matching Program
• Life Insurance (Basic, Voluntary & AD&D)
• Generous Time Off (Vacation, Sick & Public Holidays)
• Paid Family Leave
• Equity grants (applicable to full-time employees)