Sr. SOC Physical Verification Engineer (Silicon Engineering)

📋 Description

• Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools
• Develop, maintain, and optimize physical verification flows for advanced node SoC's
• Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified
• Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
• Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
• Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams

🎯 Requirements

• Bachelor's degree in electrical engineering, computer engineering or computer science
• 5+ years of ASIC and/or physical design flow development experience in industry
• Experience with SOC top level physical design flows
• Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.)
• Deep expertise in DRC, LVS, PERC and ESD verification methodologies
• Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus

🎁 Benefits

• Base salary range: $175,000 - $280,000 per year
• Long-term incentives (company stock, stock options, or long-term cash awards)
• Discretionary bonuses and Employee Stock Purchase Plan
• Comprehensive medical, vision, and dental coverage
• 401(k) retirement plan
• Short and long-term disability insurance, life insurance, paid parental leave