Sr. Staff Physical Design Engineer

📋 Description

• Implement digital blocks in advanced nodes from synthesis to verification using standard tools.
• Drive full-chip STA signoff, review constraints, debug timing reports, and implement ECOs.
• Drive power analysis and optimization balancing area and performance.
• Lead full chip floor planning, IO placement, and clock distribution.
• Understand clock details and customize clocks for functional/test clocks.
• Debug and clean up DRC/LVS.

🎯 Requirements

• Bachelor’s in Electrical Engineering or Computer Engineering
• 12+ years of industry experience as a Physical Design Engineer
• Block/top-level physical design for large ASICs or mixed-signal chips that taped out
• Thorough knowledge of timing closure, LVS/DRC closure
• Experience in TCL and Python (or other scripting languages)
• Strong teamwork skills with the ability to collaborate with multiple functional teams

🎁 Benefits

• Comprehensive Health Care Plan (Medical, Dental & Vision)
• Retirement Savings Matching Program
• Life Insurance (Basic, Voluntary & AD&D)
• Generous Time Off (Vacation, Sick & Public Holidays)
• Paid Family Leave
• Short Term & Long Term Disability