Staff Silicon Logical Design Engineer

Added
1 day ago
Type
Full time
Salary
Salary not provided

Related skills

python timing cdc synthesis systemverilog

๐Ÿ“‹ Description

  • Integrate IP and subsystems into top-level SoC designs
  • Develop and maintain build and configuration environments
  • Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level
  • Support verification and physical design teams through clean interface hand-offs
  • Debug and resolve integration-related issues across multiple hierarchies
  • Contribute to the continuous improvement of integration flows and automation

๐ŸŽฏ Requirements

  • Logical design experience in relevant industry
  • Experience range 8-12 years in Semiconductor Industry/Product development exposure
  • Be highly motivated, a self-starter, and a team player
  • Ability to work across teams and debugging issues seen to find root causes
  • Degree in Computer Science, Engineering or related subject
  • Ability to script in Python and/or TCL for automation and to solve design issues

๐ŸŽ Benefits

  • In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome
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