Minimum of 7 years working experience of FPGA code development in VHDL, Verilog and/or System
Experience of FPGA domain crossing designs
Experience of FPGA timing analyses
Experience of FPGA floorplanning
Worked with either AMD/Xilinx or Intel/Altera FPGA:s and tools such as Vivado, ISE, Quartus etc.
Competency in software scripting languages such as Python and Tcl

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