UVM Verification specialist

📋 Description

• Perform ASIC Verification using UVM and SystemVerilog
• Develop and execute test plans, test benches, and Verification environments
• Work on IP block Verification and multi-clock domain designs
• Collaborate with design teams to ensure functional correctness and coverage goals
• Apply formal Verification techniques and contribute to continuous improvement of verification
• Debug and resolve issues efficiently under tight timelines

🎯 Requirements

• Minimum 7 years of experience in ASIC/FPGA Verification
• Strong expertise in UVM methodology and SystemVerilog
• Hands-on experience with complex ASIC or large FPGA designs
• Experience in multi-clock domains and IP block Verification
• Knowledge of formal Verification tools and techniques
• Ability to create comprehensive and complex coverage models

🎁 Benefits

• Secure employment with collectively agreed terms
• Good benefits
• An organization that cares about you
• Opportunity to work on cutting-edge projects in the telecom sector
• Possibilities to gain more experience across different industries