Design Verification Lead

📋 Description

• Develop and execute comprehensive design verification strategies and plans for IP and SoC projects.
• Translate functional and technical requirements into detailed verification plans, test scenarios
• Develop scalable and reusable SystemVerilog/UVM verification environments.
• Build UVM components including testbenches, agents, drivers, monitors, sequencers, scoreboards, and
• Set up, configure, execute, and debug functional and gate-level simulations.
• Develop and maintain automated regression environments for large verification programs.

🎯 Requirements

• 7+ years of professional experience in ASIC, SoC, IP, or semiconductor design verification.
• Proven experience executing at least 3 IP or SoC verification projects from planning through
• Strong hands-on expertise in SystemVerilog and UVM methodology.
• Experience developing and maintaining reusable UVM-based verification environments.
• Strong experience translating functional requirements into verification plans and test strategies.
• Hands-on experience setting up and debugging functional and/or gate-level simulations.