Senior Silicon Verification Engineer

📋 Description

• Verification planning, specification, and closure of functional coverage
• Provide feedback to architects on verification issues
• Generate tests and perform failure diagnosis/triage
• Contribute to shared verification infrastructure
• Ensure good communication between sites

🎯 Requirements

• Verification experience in relevant industry
• Proven leadership and planning skills
• Self-starter and team player
• Experience with CPU and/or ASIC verification
• System Verilog, Python, C++, Linux
• UVM, SVA, DVCS (e.g., Git), XML/XPath

🎁 Benefits

• Competitive benefits package
• Equal opportunity employer
• Flexible interview approach