Staff Engineer - Design Verification

📋 Description

• Define verification strategy and architecture for PCIe, CXL, Ethernet, and UCIe subsystems.
• Architect and develop layered UVM environments, testbenches, and verification components for
• Drive verification of PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, and UCIe PHY/Adapter layers.
• Lead coverage-driven verification, functional coverage closure, assertion-based verification (SVA)
• Lead debugging across simulation, emulation, prototyping, and silicon bring-up; mentor junior/mid
• Collaborate with design, architecture, and validation teams to mitigate risks and deliver robust

🎯 Requirements

• 8+ years of professional Design Verification experience with complex SoC/IP verification.
• Bachelors or Masters in Electrical/Computer Engineering or related field.
• Proven ability to define/deploy verification architectures for high-speed interfaces/protocols.
• Strong hands-on expertise in SystemVerilog, UVM, coverage-driven verification, and SystemVerilog
• Deep experience with PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G or similar tech.
• Strong understanding of UCIe PHY/Adapter verification is highly desirable.

🎁 Benefits

• Remote-friendly opportunity for candidates based in India.
• Ownership over verification architecture and methodology for AI/ HPC semiconductor ecosystems.
• Exposure to chiplet, high-speed interconnect, and custom silicon technologies.
• Opportunity to work on challenging PCIe, CXL, Ethernet, and UCIe protocols.
• Global collaboration with experienced semiconductor engineers in India and the US.
• Fast-paced environment with emphasis on technical execution and reusable verification frameworks.