Senior FPGA & Firmware Engineer - SDR

📋 Description

• Research, model, and implement industry-leading SDR and digital communications algorithms — OFDM
• Develop floating- and fixed-point behavioral reference models in MATLAB/Simulink, make quantization
• Generate and integrate RTL from Simulink using HDL Coder, and author hand-written VHDL/Verilog
• Implement designs in Vivado through the full flow — synthesis, place-and-route, and timing closure
• Architect and implement on-chip interfaces and data movement: AXI4 / AXI4-Stream, DMA, register
• Build and maintain rigorous verification: Simulink/HDL co-simulation, bit-true comparison against

🎯 Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a similar engineering
• 6+ years of industry FPGA/RTL design experience taking digital logic from architecture through
• Highly proficient in RTL design with VHDL and/or Verilog/SystemVerilog, including synthesizable
• Strong hands-on proficiency with the Xilinx/AMD Vivado toolchain — synthesis, implementation
• Demonstrated experience with MATLAB and Simulink for algorithm modeling, and with model-based
• Solid foundation in digital signal processing and digital communications: sampling, filtering

🎁 Benefits

• Competitive salary and 401k with employer match
• Discretionary paid time off
• Paid parental leave for all
• Medical, Dental, Vision plans
• Fitness Programs
• Emotional & Mental Wellness support